Many computing platforms or systems employ a graphics processor as a subsystem that performs image processing/rendering and/or parallel computation. A graphics processor may consume large amounts of power. Mobile computing platforms operating under stringent power constraints (e.g., to maximize battery charge duration) typically attempt to manage graphics power and performance controls, for example by placing various components of the computing system in different performance states. Conventional power management algorithms may however perform poorly in use cases where multiple applications are sending workloads to a graphics processor concurrently, for example in platforms operating in partial-screen and/or multi-display modes.
Also, many graphics power management systems today entail a number of algorithms and systems that independently attempt to improve specific aspects of power efficiency, operating as a patchwork rather than a cohesive unit. With no clear ownership of power-performance controls, current solutions rely on inter-algorithm communication to prevent graphics processor resource access conflicts. As such, it is left to the developer of each algorithm to track dependencies with supplemental algorithms, a problem that increases in complexity with each new power management algorithm introduced. Competition between algorithms further complicates integrating new techniques into a power management architecture as competition between algorithms becomes more likely.
A graphics processing subsystem that is able to achieve greater power efficiency and/or unify the graphics power management architecture would therefore be advantageous in the marketplace.